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Identifying Compiler Options to Minimize Energy Consumption by Embedded Programs[edit]

This project is under the supervision of Jeremy Bennett[1] and Simon Hollis[2].

The broad goal of this project is to find which compiler optimizations affect the energy consumption of a program. This is an open community project, and anyone with an interest in low power embedded software development is invited to contribute their ideas through this Wiki. The results will be published in an open access journal, and so be freely available to all.

This project was kicked off with a presentation to the GCC Cauldron on 9th July. Several embedded architectures are targeted - mostly development boards modified with fine-grained hardware energy measurement devices:

  • ARM Cortex M0 [3]
  • ARM Cortex M3 [4]
  • ARM Cortex A8 [5]
  • MIPS32 [6]
  • XMOS L1 Series [7]
  • Adapteva Epiphany Board [8]

Questions we'd like to answer:

  • Which set of benchmarks are suitable for embedded applications and representative of possible applications?
  • What compiler options have the most effect on the power consumption of the device?
  • Does choice of compiler make any difference (LLVM or GCC)?
  • Does optimizing for speed give the same results as optimizing for energy usage?
  • Does choice of architecture make a difference?


The full conclusions are available. The main conclusions:

  • Time≈energy
  • It is not possible to predict which optimizations will be effective
  • There is not one flag which is optimal for all platforms/benchmarks

The results have been written up into two papers describing the benchmarks (link todo) and the results (link todo). All of the data is made available via the results page.

Project Timeline[edit]

This section describes the current progress with the project.

Week 1 Currently most work has been done under the benchmarks section, evaluating different suites for their ease of portability and suitability to the project.
Week 2 The final set of benchmarks has been identified.
Week 3 Soldering and bringing up the power measurement boards
Week 4 Porting the benchmarks and starting the test harness
Week 5 Two of the platforms are currently hooked up to the harness and taking energy measurements
Week 6-9 The Cortex-M0, Cortex-M3, Cortex-A8, Epiphany Board, and XMOS board are hooked up and taking measurements
Week 10-12 The results are currently being written up.


Some details about the Project Plan are available, as well as Literature.

A comprehensive overview of the Benchmarks is available. This lists all of the suites examined, individual benchmarks and the strengths and weaknesses of each. A final set of benchmarks is picked to cover different criteria.

Fractional factorial designs are used to explore compiler options, compensating for the interaction effects. More information at Experimental Design and Compilers.

Extra Pages[edit]

GCC Cauldron Low Power Notes

Power Measurement Circuitry

Initial Energy Measurements